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Tips for HVL and HDL users with special emphasis on Specman-e, SystemVerilog and Questa
Specman Verification
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An internet riddle... 
Saturday, April 28, 2007, 02:29 AM - Personal
I just got an email from a guy named Raven who runs a website and would like link to me from his page. A quick search on the internet showed that he's been running a website named www.myairshoes.com, dedicated to Nike Air. I learned there for example, that Nike are about to release a superbly ugly Nike Air Oktoberfest version...what this has got to do with verification, only god knows, but I guess [s]he does because after a few more minutes of searching I learned that Raven is a "21 year old Christian blogger", and that he's been sending similar emails to a whole bunch of websites, with diverse interests ranging from lesbian rights and old french armoires. I also found the following quite funny reply to his sort of standard email...I hope these guys will not ask me to provide the same stuff...

As you can see, its Saturday morning and I've got a lot of time on my hands.

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Questa's bugged debugger 
Monday, April 23, 2007, 03:07 AM - The verification hood
These last few weeks I have been having a sneaking suspicion that Questasim’s SystemVerilog debugging abilities are far from perfect. A kind of hunch, based on the fact that things were never where I expected them to…so, for your sake, my dear readers, I've decided to lie on the barbed wire, “read the Questasim manual”, prove or disprove my gut feeling, and provide you with an executive summary of the results.

Here are some of the problems I had. To begin with, while it is possible to open the source code for any static item (i.e. module) by clicking on it in the structure window, I have not been able to do the same thing with classes. So, putting a breakpoint on a class function required me to use the regular “open file” interface. This can very easily get on your nerves after a while. Once I was able to finally get to the class code, many of the executable lines were marked as non executable so you couldn’t break on them. And, once I did find a line to “rest” my breakpoint on, I was not able to examine the values of any class variables, in either the “locals” or the “watch” window. In a module function/task they would be visible at the “locals” window. I also noticed some strange behaviour when I was running code step by step, but wasn’t really able to say what it was. Seems like in some cases the “step into” and “step over” buttons simply result in a “run –all”. Finally I have not been able to find the calling stack anywhere around the place. I can hear you snoring already so I’ll stop right there.

I took sometime to double check that none of these problems was the result of my “eastern imagination” then moved on to the user manual. Going over the relevant part took me no-time as it has so surprisingly little to say about SV code debugging. The following paragraph, taken from the so called “verification with systemverilog” chapter, might explain why the user manual is so mute:

"This chapter discusses the QuestaSim implementation of SystemVerilog verification features. The chapter is more-or-less divided into two halves. The first half discusses SystemVerilog assertions including both assert and cover directives. The second half discusses SystemVerilog functional coverage as implemented by covergroups, coverpoints, and the like. A small section at the end discusses randomization and testbench automation."

So, for Mentor SystemVerilog for verification means first of all assertions and coverage. No wonder you can’t find anything regarding sequential code. This reminded me of a comment from JL about the big EDA companies dedicating much more attention to coverage rather then generation and checking. Which is quite worrying if you ask me…

And which is why, the manual does not provide any valuable information about any of the issues mentioned above. In fact, I couldn’t even find a simple window that would show class variables or local variables within a class function/task. Neither the “watch” or the “locals” window documentation, mention any support of SystemVerilog classes, and this is in fact, as I said above, evident in real-life as well. So, until someone realizes that SV sequential code has its place as well, we will probably just have to guess. Or, maybe all of this will be solved by itself with Questasim 6.4?

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Questasim - an IDE or a simulator? 
Friday, April 20, 2007, 03:43 AM - The verification hood
I'm starting to get the feeling that despite the move to SV, Questasim is still a simulator rather then an IDE (Integrated Development Environment) for OO code. Objects other then modules, like class instances, just don't get treated right (in Big Lebowski words: "They treat objects like women")...for example, I haven't found a nice and easy way to open files that contain class definitions, when you'd like to place a breakpoint on one of the lines. The way I'm using now is just the regular "open file" interface, which just gets on my nerves. In normal IDEs, double clicking on a class instance should open the code for the class...

In fact, I suspect there is a bug here because even the "view declaration" menu option for fields within a class doesn't work.

If you have the solution please let me know...
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