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Tips for HVL and HDL users with special emphasis on Specman-e, SystemVerilog and Questa
Specman Verification
Verification engineer? Verifigen has the right project for you!
SystemVerilog source bank 
Saturday, April 7, 2012, 09:51 AM - Hardcore verification
This is an experiment, that I'm mainly conducting to help myself. In the next weeks/months I hope to start uploading SystemVerilog code and examples that are available on the web. UVM-1.1, which I luckily saved on my laptop before it went off the web, is the avant-garde.

One of the most useful pages is of course, UVM's own help, which is available here. This is the respective page for OVM.

Many thanks to Sandy Hefftz for her help with this one.

Available code:

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Me @ DVCon 
Friday, April 6, 2012, 05:57 AM - Hardcore verification
In the latest months all my writing energy, in fact, all my energy, was consumed by two DVCon papers, that I can now share with you. The first, is about SV and UVM random stability, a subject which, surprisingly enough, no one ever wrote about in the past. It opens with a crash course on random stability in SystemVerilog, and then moves on to explore UVMís random stability infrastructure and some problems and possible solutions. If youíre looking for some more user-friendly material than IEEE-1864 and the non-existent UVM documentation on the subject, you are in the right place.

The second paper was harder and more demanding to write, but Iím sure some of this blogís readers will find it helpful as well. It deals with e/eRM to SV/UVM migration, and will help anyone who is about to go through this process understand better the challenges, and plan for the best solutions upfront. It contains many cool tips and code examples that show how to implement them. It will also help you do your SystemVerilog signal mapping just like you used to do when you were using Specman/e (i.e. by specifying strings to ďhdl_path()Ē, with a package that Iím especially proud of.

You can find both paperís here:

UVM Random Stability - don't leave it to chance
e/eRM to SystemVerilog/UVM - mind the gap but don't miss the train

And hereís the poster I prepared for the random stability paper presentation, just in case youíre looking to replace Elvis on your bedroom wall:

UVM Random Stability poster
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Add color to your UVM environment 
Monday, December 26, 2011, 08:35 AM - Hardcore verification
This is the tiniest contribution ever made to UVM but its usefullness is inverse proportional to its size. It Allows you to color all messages coming from a specific block or environment in your UVM testbench. The colors will be visible in a batch mode run, so you can use it to make log files dumped by regression more readable. In fact, this is exactly what I've created it for. Enjoy!

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