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Greping all loaded e files for a regex 
Friday, October 2, 2009, 05:13 AM - Hardcore verification
Warning: This entry was extensively modified since it was first published about two weeks ago. Many good people, more than I thought were reading this blog, have pointed out mistakes, inaccuracies, and outright lies in the ~20 lines I wrote. After I got one or two lawsuit threats I finally decided to rewrite it ;-)

When originally posted, this entry started with the sentence "For some reason that escapes me, Specman's 'search' command will only look for a regular string in the e files in your testbench, but not for a regular expression". While this sentence is true (i.e. when you type "search" at Specman's command line you can only give a string as a parameter), it is absolutely not true that you can't do a regex search from within Specman itself: Pushing Specman's GUI search button will take you to a search screen where you can look for regular expressions or for regular strings inside type definitions, constraints and what not. The search is preformed, needless to say, in all the currently loaded e modules.

If, like me, you're working for a company that doesn't have an all-you-can-eat deal with Cadence, then probably you don't want to take a license every time you want to search your e files. To search the e modules in your testbench for regular expressions and strings offline, you can use the perl script below to extract a list of e files from your specman.elog file, then use this file list with grep. This will require you to run Specman only once, so that you have a specman.elog file where all the files in your testbench are imported: the stubs creation stage will do for this purpose. Once the file list is created, here are some useful greps you can use it with:

grep "field_name.*\:" `cat modules.txt` #will take you to the field definition (and maybe to one or two other garbage places)
grep "\:.*field_type" `cat modules.txt` #will take you to all the places where a field of a certain type is defined
grep "port_name.*hdl_path" `cat modules.txt` #will take you to the place where a port is tied to its hdl path.
grep "struct[ ]+[a-zA-Z0-9_]+" `cat modules.txt` #will look for all struct definitions

But why write your greps alone if you can get David Robinson to borrow you his? Verilab's great e toolkit, written by David, will look for just about anything you might want in the list of files you feed it with, and print the results nicely formatted to your screen. This will save you the headache of coming up with the correct regular expression for whatever you're looking for. The toolkit will also do some wonderfully useful things such as collecting all the class or enum extensions from your files, or printing the "like" inheritance hierarchy. In short, it will do everything you can do from Specman and more.

Many thanks to Corey Goss from Cadence for his feedback, David Robinson from Verilab for pointing me to the toolkit, Pini Krengel who provided the original version of the script below and Ran Karen who knows everything about Specman, for their help with this post. God, I hope I made everyone happy and won't have to rewrite it again...


open(MODULE_LIST, ">modules.txt") || die $!;


  local $/=undef;

  open LOG, "specman1.elog" or die "Couldn't open file: $!";

  binmode LOG;

  $log = ;

  # turn cyclic imports into normal import form

  $log =~ s/\n/ /g;

  $log =~ s/Loading \(([^\)]*)\)/Loading $1/g;

  $log =~ s/ \+ ([^ ]*)/Loading $1/g;

  $log =~ s/Loading/\nLoading/g;

  # match normal imports

  my $normal_import_match_string = '^Loading[ |\n]([^ ]+\\.e)';

  my @evc_files;

  if(@evc_files = $log =~ /$normal_import_match_string/smg) {

    foreach $evc_file (@evc_files) {

      print MODULE_LIST "$evc_file" . "\n";






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Parsing Verilog using Perl (out of boredom) 
Saturday, September 26, 2009, 06:31 AM - Hardcore verification
I've always suspected that boredom, not money, power, sex or anything else, is what makes the world go around and after 3 weeks of unemployment, now finally behind me, I am at last able to confirm this suspicion. In search of something meaningful to do with my time between the beach, the Israeli version of Survivor, and some occasional meetings with potential employers, I decided to pursue an idea I had some time ago, and try to implement it myself. This took me into an unexpected direction of trying to figure out what's the best way of parsing Verilog files. It is hard to say at this stage where my idea will end up, but as a by-product I got some short useful insights and some real code for anyone who intends to use Perl to look into the entrails of a Verilog file...

Starting with google, a simple search of "perl verilog parser" will immediately take you to a package called Verilog::Parser, and another package called v2html. Using these ready-made packages is an easy way to go, but you have to be aware that both of them will hide out a lot of information that you might want to have. Verilog::Parser, for example, breaks a Verilog file into atoms such as keywords, tokens, and numbers and gives you a callback for each. However, if you want to look for something bigger, say, a complete "always" block, you will find yourself re-parsing these atoms into blocks, which is not an easy task. Since my idea required a more high-level point of view, I decided to look for something else.

The next step, therefore, was to dump Verilog::Parser and v2html, and just look at parsing files with Perl. I was assuming that Perl has something generic to offer here, since almost every second programmer, uses Perl exactly for this kind of task. And in fact, Perl does have a very cool and well documented package called Parse::RecDescent, which will parse any file according to any BNF grammar you provide, and enable you to preform custom things for any production it sees on its way. Verilog's BNF can be found here, and in a version that can be easily converted into what Perl's RecDescent would eat, right here. This last link leads to a page under ANTLR's website, and I'll go back to talk about ANTLR in a second.

After adapting the grammar to Perl and installing RecDescent, I was ready to go, and although I still have some difficulties implementing my idea, they're much smaller compared to the ones I had to deal with before...If you think this might be useful for you as well, you can download my Verilog grammer for Perl's RecDescent, and a small example, right here.

As mentioned above I adapted the Perl RecDescent Verilog grammer from a grammer I found on ANTLR's site. This, of course, made me curious about what ANTLR was, and I soon found out it was a very cool free IDE for debugging grammar's and building compilers. For example, it can give you a graphical representation of any grammer you load into it, which can be very helpful when you're trying to figure out how a rule is broken down into individual productions all the way to the individual identifiers. It also has an active user community which had helped me patiently with some stupid questions I had. It is worth trying out...

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No comments! 
Monday, August 17, 2009, 11:04 AM - Hardcore verification
Due to an annoying spam comments attack I've decided to disable comments for a while. Please feel free to contact me directly with anything you would like to say at avidan_e at yahoo dot com.
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